Datasheet

Serial Peripheral Interface (SPI)
Register Descriptions
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
MODF — Mode Fault Flag
This bit is set if the SS
input becomes low while the SPI is configured
as a master. The flag is cleared automatically by a read of the SPI
status register (with MODF set) followed by a write to the SPI control
register 1. The MODF flag is set only if the MODFEN bit of SPICR2
register is set, Refer to MODFEN bit description in SPI Control
Register 2 (SPICR2).
1 = Mode fault has occurred.
0 = Mode fault has not occurred.
SPI Data Register
(SPIDR)
Read: anytime; normally read only after SPIF is set
Write: anytime; see SPTEF
The SPI Data register is both the input and output register for SPI
data. A write to this register allows a data byte to be queued and
transmitted. For a SPI configured as a master, a queued data byte is
transmitted immediately after the previous transmission has
completed. The SPI Transmitter empty flag in SPISR indicates when
the SPI data register is ready to accept new data.
NOTE: Do not write to the SPI data register unless the SPTEF bit is high.
Reading the data can occur anytime from after the SPIF is set to
before the end of the next transfer. If the SPIF is not serviced by the
end of the successive transfers, those data bytes are lost and the data
within the SPIDR retains the first byte until SPIF is serviced.
Address Offset: $0005
Bit 7 6 5 4 3 2 1 Bit 0
R
Bit 7 6 5 4 3 2 2 Bit 0
W
Reset: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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