Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
SPI Status Register
(SPISR)
Read: anytime
Write: has no meaning or effect
SPRF — SPRF Receive Interrupt Flag
This bit is set after the eighth SCK cycle in a data transfer and is
cleared by reading the SPISR register (with SPIF set) followed by a
read access to the SPI data register.
1 = New data Copied to SPIDR
0 = Transfer not yet complete
SPTEF — SPI Transmit Empty Interrupt Flag
This bit is set each time the transmit data register transfers a byte into
the shift register. SPTEF generates an SPTEF CPU interrupt request
if the SPTIE bit in the SPICR1 is also set.This bit is cleared by reading
the SPISR register (with SPTEF set) followed by a write access to the
SPI data register.For an idle master or idle slave that has no data
loaded into its transmit buffer, the SPTEF will be set again within two
bus cycles since the transmit buffer empties into the shift register.
This allows the user to queue up 16-bit value to send. For an already
active slave, the load of the shift register cannot occur until the
transmission is complete.The SPTEF indicates when the next write
can occur
1 = SPI Data register empty
0 = SPI Data register not empty
Address Offset: $0003
Bit 7 6 5 4 3 2 1 Bit 0
R SPRF 0 SPTEF MODF 0 0 0 0
W
Reset: 001 0 0 0 0 0
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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