Datasheet

Serial Peripheral Interface (SPI)
Register Descriptions
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
SPI Baud Rate
Register (SPIBR)
Read: anytime
Write: anytime; writes to unimplemented bits have no effect
NOTE: Writing to this register during data transfers may cause spurious results
SPPR2–SPPR0 — SPI Baud Rate Preselection Bits
SPR2–SPR0 — SPI Baud Rate Selection Bits
These bits specify the SPI baud rates as shown in the table below
The baud rate divisor equation is as follows
Table 77 Bidirectional Pin Configurations
Pin Mode SPC0 MSTR
MISO
(1)
1. Slave output is enabled if BIDIROE bit = 1, SS = 0, and MSTR = 0 (C)
MOSI
(2)
2. Master output is enabled if BIDIROE bit = 1 and MSTR = 1 (D)
SCK
(3)
3. SCK output is enabled if MSTR = 1 (B, D)
SS
(4)
4. SS output is enabled if MODFEN bit = 1, SSOE = 1, and MSTR = 1 (B, D).
A
Normal 0
0 Slave Out Slave In SCK in SS in
B 1 Master In Master Out SCK out SS I/O
C
Bidirectional 1
0 Slave I/O --- SCK in SS In
D 1 --- Master I/O SCK out SS I/O
Address Offset: $0002
Bit 7 6 5 4 3 2 1 Bit 0
R 0
SPPR2 SPPR1 SPPR0
0
SPR2 SPR1 SPR0
W
Reset: 000 0 0 0 0 0
= Unimplemented or Reserved
BaudRateDivisor SPPR 1+()2•
SPR 1+()
=
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