Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
SPI Control
Register 2 (SPICR2)
Read: anytime
Write: anytime; writes to unimplemented bits have no effect
MODFEN — Mode Fault Enable Bit
This bit when set allows the MODF flag to be set. If the MODF flag is
set, clearing the MODFEN does not clear the MODF flag. If the SPI is
enabled as master and the MODFEN bit is low, then the SS
is
available as a general purpose I/O.
When the SPI is enabled as a slave, the SS is available only as an
input regardless of the value of MODFEN.
1 = Enable setting the MODF error
0 = Disable the MODF error
BIDIROE — Output enable in the Bidirectional mode of operation
This bit along with the MSTR bit of SPCR1 is used to enable the
output buffer when the SPI is configured in bidirectional mode.
1 = Output buffer enabled
0 = Output buffer disabled
SPISWAI — SPI Stop in Wait Mode Bit
This bit is used for power conservation while in wait mode.
1 = Stop SPI clock generation when in wait mode
0 = SPI clock operates normally in wait mode
SPC0 — Serial Pin Control Bit 0
With the MSTR control bit, this bit enables bidirectional pin
configurations as shown in Table 77.
Address Offset: $0001
Bit 7 6 5 4 3 2 1 Bit 0
R 0 0 0
MODFEN BIDIROE
0
SPISWAI SPC0
W
Reset: 000 0 0 0 0 0
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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