Datasheet

Serial Peripheral Interface (SPI)
Register Descriptions
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
MSTR — SPI Master/Slave Mode Select Bit
1 = Master mode
0 = Slave mode
CPOL — SPI Clock Polarity Bit
This bit selects an inverted or non-inverted SPI clock. To transmit data
between SPI modules, the SPI modules must have identical CPOL
values.
1 = Active-low clocks selected; SCK idles high
0 = Active-high clocks selected; SCK idles low
CPHA — SPI Clock Phase Bit
This bit is used to shift the SCK serial clock.
1 = The first SCK edge is issued at the beginning of the 8-cycle
transfer operation
0 = The first SCK edge is issued one-half cycle into the 8-cycle
transfer operation
SSOE — Slave Select Output Enable
The SS output feature is enabled only in the master mode by
asserting the SSOE as shown in Table 76.
LSBFE — SPI LSB-First Enable
This bit does not affect the position of the msb and lsb in the data
register. Reads and writes of the data register always have the msb
in bit 7.
1 = Data is transferred least significant bit first.
0 = Data is transferred most significant bit first.
Table 76 SS
Input / Output Selection
MOD
FEN
SSOE Master Mode Slave Mode
0 0 ---- SS input
0 1 ---- SS input
10SS input with MODF feature SS input
11 SS output SS input
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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