Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Register Descriptions
This section consists of register descriptions in address order. Each
description includes a standard register diagram with an associated
figure number. Details of register bit and field function follow the register
diagrams, in bit order.
SPI Control
Register 1 (SPICR1)
Read: anytime
Write: anytime
SPIE — SPI Interrupt Enable Bit
This bit enables SPI interrupts each time the SPIF or MODF status
flag is set.
1 = SPI interrupts enabled.
0 = SPI interrupts disabled.
SPE — SPI System Enable Bit
This bit enables the SPI system and dedicates the SPI port pins to SPI
system functions. When SPE is clear, the SPI system is initialized but
in a low-power disabled state.
1 = SPI port pins are dedicated to SPI functions.
0 = SPI system is in a low-power, disabled state.
SPTIE — SPI Transmit Interrupt Enable
This bit enables SPI interrupt generated each time the SPTEF flag is
set.
1 = SPTEF interrupt enabled.
0 = SPTEF interrupt disabled.
Address Offset: $0000
Bit 7 6 5 4 3 2 1 Bit 0
R
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W
Reset: 0 0 0 0 0 1 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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