Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Peripheral Interface (SPI)
Register Quick Reference
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Register Quick Reference
Figure 81 SPI Register Summary
Register Name Bit 7 6 5 4 3 2 1 Bit 0
Address
Offset
SPICR1
R
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE $0000
W
SPICR2
R 0 0 0
MODFEN BIDIROE
0
SPISWAI SPC0 $0001
W
SPIBR
R 0
SPPR2 SPPR1 SPPR0
0
SPR2 SPR1 SPR0 $0002
W
SPISR
R SPRF 0 SPTEF MODF 0 0 0 0
$0003
W
SPI Reserved
R 0 0 0 0 0 0 0 0
$0004
W
SPIDR
R
Bit 7 6 5 4 3 2 1 Bit 0 $0005
W
SPI Reserved
R 0 0 0 0 0 0 0 0
$0006
W
SPI Reserved
R 0 0 0 0 0 0 0 0
$0007
W
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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