Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Normally this signal is asserted when the SPE bit of the SPICR1 register
is set. Also, when configured in Slave mode and in Bidirectional mode of
operation, this signal is de-asserted.
Miso port enable
(miso_port_en)
This pin indicates that the SPI is the master of the MISO pad.
Normally this signal is asserted when the SPE bit of the SPICR1 register
is set.Also, when configured in Master mode and in Bidirectional mode
of operation, this signal is de-asserted.
SS port enable
(ss_port_en)
This pin indicates that the SPI is the master of the SS pad.
Normally this signal is asserted when the SPE bit of the SPICR1 register
is set. When configured in Master mode and MODFEN bit of SPICR2 is
cleared, then this signal is de-asserted.
Sck port enable
(sck_port_en)
This pin indicates that the SPI is the master of the SCK pad. Normally
this signal is asserted when the SPE bit of the SPICR1 register is set.
Mosi port output
enable
(mosi_obe)
This pin indicates that the MOSI output buffer is enabled if mosi_port_en
was set.
If the bidirectional serial pin mode is selected in the master, MOSI
becomes MOMI (master out/master in) and the direction is controlled by
the BIDIROE bit 3 of the SPI control register 2.
Miso port output
enable
(miso_obe)
This pin indicates that the MISO output buffer is enabled if miso_port_en
was set.
If the bidirectional serial pin mode is selected in the slave, MISO
becomes SISO (slave in/slave out) and the direction is controlled by the
BIDIROE bit 3 of the SPI control register 2.
SS port output
enable (ss_obe)
This pin indicates that the SS output buffer is enabled if ss_port_en was
set.
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Freescale Semiconductor, Inc.
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