Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Features
The Serial Peripheral Interface includes these distinctive features:
• Master mode and slave mode
• Bi-directional mode
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Double-buffered operation
• Serial clock with programmable polarity and phase
• Control of SPI operation during wait mode
Modes of Operation
The SPI functions in three modes, run, wait, and stop.
• Run Mode
This is the basic mode of operation.
• Wait Mode
SPI operation in wait mode is a configurable low power mode.
Depending on the state of internal bits, the SPI can operate
normally when the CPU is in wait mode or the SPI clock
generation can be turned off and the SPI module enters a power
conservation state during wait mode. During wait mode, any
master transmission in progress stops. Reception and
transmission of a byte as slave continues so that the slave is
synchronized to the master.
• Stop Mode
The SPI is inactive in stop mode for reduced power consumption.
The STOP instruction does not affect or depend on SPI register
states. Again, reception and transmission of a byte as slave
continues to stay synchronized with the master.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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