Datasheet

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
operation) and all the following interrupts, when generated, are ORed
together and issued through that port.
TDRE Description The TDRE interrupt is set high by the SCI when the transmit shift register
receives a byte from the SCI data register. A TDRE interrupt indicates
that the transmit shift register (SCIDRH/L) is empty and that a new byte
can be written to the SCIDRH/L for transmission.Clear TDRE by reading
SCI status register 1 with TDRE set and then writing to SCI data register
low (SCIDRL).
TC Description The TC interrupt is set by the SCI when a transmission has been
completed. A TC interrupt indicates that there is no transmission in
progress. TC is set high when the TDRE flag is set and no data,
preamble, or break character is being transmitted. When TC is set, the
TXD pin becomes idle (logic 1). Clear TC by reading SCI status register
1 (SCISR1) with TC set and then writing to SCI data register low
(SCIDRL). TC is cleared automatically when data, preamble, or break is
queued and ready to be sent.
RDRF Description The RDRF interrupt is set when the data in the receive shift register
transfers to the SCI data register. A RDRF interrupt indicates that the
received data has been transferred to the SCI data register and that the
byte can now be read by the MCU. The RDRF interrupt is cleared by
reading the SCI status register one (SCISR1) and then reading SCI data
register low (SCIDRL).
OR Description The OR interrupt is set when software fails to read the SCI data register
before the receive shift register receives the next frame. The newly
acquired data in the shift register will be lost in this case, but the data
already in the SCI data registers is not affected. The OR interrupt is
cleared by reading the SCI status register one (SCISR1) and then
reading SCI data register low (SCIDRL).
IDLE Description The IDLE interrupt is set when 10 consecutive logic 1s (if M=0) or 11
consecutive logic 1s (if M=1) appear on the receiver input. Once the
IDLE is cleared, a valid frame must again set the RDRF flag before an
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