Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Interrupt Operation
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Stop Mode The SCI is inactive during stop mode for reduced power consumption.
The STOP instruction does not affect the SCI register states, but the SCI
module clock will be disabled. The SCI operation resumes from where it
left off after an external interrupt brings the CPU out of stop mode.
Exiting stop mode by reset aborts any transmission or reception in
progress and resets the SCI.
Interrupt Operation
Recovery from
Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait
mode.
System Level
Interrupt Sources
This section describes the interrupt originated by the SCI block.The
MCU must service the interrupt requests. Table 73 lists the five interrupt
sources of the SCI. The local enables for the five SCI interrupt sources,
are described in Table 73.
The SCI only originates interrupt requests. The following is a description
of how the SCI makes a request and how the MCU should acknowledge
that request. The interrupt vector offset and interrupt number are chip
dependent. The SCI only has a single interrupt line (sci_int, active high
Table 73 SCI Interrupt Sources
Interrupt Source Description
TDRE SCISR1[7]
Active high level detect. Indicates that a
byte was transferred from SCIDRH/L to
the transmit shift register.
TC SCISR1[6]
Active high level detect. Indicates that a
transmit is complete.
RDRF SCISR1[5]
Active high level detects. The RDRF
interrupt indicates that received data is
available in the SCI data register.
OR SCISR1[3]
Active high level detects. This interrupt
indicates that an overrun condition has
occurred.
IDLE SCISR1[4]
Active high level detect. Indicates that
receiver input has become idle.
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