Datasheet

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
.
Figure 78 Loop Operation (LOOPS = 1, RSRC = 0)
Enable loop operation by setting the LOOPS bit and clearing the RSRC
bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables
the path from the sci_rx_ind signal to the receiver. Clearing the RSRC
bit connects the transmitter output to the receiver input. Both the
transmitter and receiver must be enabled (TE = 1 and RE = 1).
Modes of Operation
Run Mode Normal mode of operation.
Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in
the SCI control register 1 (SCICR1).
• If SCISWAI is clear, the SCI operates normally when the CPU is
in wait mode.
• If SCISWAI is set, SCI clock generation ceases and the SCI
module enters a power-conservation state when the CPU is in wait
mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
If SCISWAI is set, any transmission or reception in progress stops
at wait mode entry. The transmission or reception resumes when
either an internal or external interrupt brings the CPU out of wait
mode. Exiting wait mode by reset aborts any transmission or
reception in progress and resets the SCI.
RXD
TRANSMITTER
RECEIVER
sci_tx_do
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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