Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
receiver interrupts are disabled.The SCI will still load the receive data
into the SCIDRH/L registers, but it will not set the RDRF flag.
The transmitting device can address messages to selected receivers by
including addressing information in the initial frame or frames of each
message.
The WAKE bit in SCI control register 1 (SCICR1) determines how the
SCI is brought out of the standby state to process an incoming message.
The WAKE bit enables either idle line wakeup or address mark wakeup.
Idle input line
wakeup
(WAKE = 0)
In this wakeup method, an idle condition on the sci_rx_ind signal clears
the RWU bit and wakes up the SCI. The initial frame or frames of every
message contain addressing information. All receivers evaluate the
addressing information, and receivers for which the message is
addressed process the frames that follow. Any receiver for which a
message is not addressed can set its RWU bit and return to the standby
state. The RWU bit remains set and the receiver remains on standby
until another idle character appears on the sci_rx_ind signal.
Idle line wakeup requires that messages be separated by at least one
idle character and that no message contains idle characters.
The idle character that wakes a receiver does not set the receiver idle
bit, IDLE, or the receive data register full flag, RDRF.
The idle line type bit, ILT, determines whether the receiver begins
counting logic 1s as idle character bits after the start bit or after the stop
bit. ILT is in SCI control register 1 (SCICR1).
Address mark
wakeup
(WAKE = 1)
In this wakeup method, a logic 1 in the most significant bit (msb) position
of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the
msb position marks a frame as an address frame that contains
addressing information. All receivers evaluate the addressing
information, and the receivers for which the message is addressed
process the frames that follow. Any receiver for which a message is not
addressed can set its RWU bit and return to the standby state. The RWU
bit remains set and the receiver remains on standby until another
address frame appears on the sci_rx_ind signal.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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