Datasheet

Serial Communications Interface (SCI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Fast Data
Tolerance
Figure 76 shows how much a fast received frame can be misaligned.
The fast stop bit ends at RT10 instead of RT16 but is still sampled at
RT8, RT9, and RT10.
Figure 76 Fast Data
For an 8-bit data character, data sampling of the stop bit takes the
receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 76, the receiver counts
154 RT cycles at the point when the count of the transmitting device is
10 bit times x 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is:
((154 – 160) / 154) x 100 = 3.90%
For a 9-bit data character, data sampling of the stop bit takes the
receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 76, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
11 bit times x 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 9-bit character with no errors is:
((170 – 176) / 170) x 100 = 3.53%
Receiver Wakeup To enable the SCI to ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCI control
register 2 (SCICR2) puts the receiver into a standby state during which
IDLE OR NEXT FRAMESTOP
RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
RT10 RT11 RT12 RT13 RT14 RT15 RT16
DATA
SAMPLES
RECEIVER
RT CLOCK
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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