Datasheet

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Slow Data
Tolerance
Figure 75 shows how much a slow received frame can be misaligned
without causing a noise error or a framing error. The slow stop bit begins
at RT8 instead of RT1 but arrives in time for the stop bit data samples at
RT8, RT9, and RT10.
Figure 75 Slow Data
For an 8-bit data character, data sampling of the stop bit takes the
receiver 9 bit times x 16 RT cycles +10 RT cycles =154 RT cycles.
With the misaligned character shown in Figure 75, the receiver counts
154 RT cycles at the point when the count of the transmitting device is 9
bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit data character with no errors is:
((154 – 147) / 154) x 100 = 4.54%
For a 9-bit data character, data sampling of the stop bit takes the
receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 75, the receiver counts
170 RT cycles at the point when the count of the transmitting device is
10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is:
((170 – 163) / 170) x 100 = 4.12%
MSB STOP
RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
RT10 RT11 RT12 RT13 RT14 RT15 RT16
DATA
SAMPLES
RECEIVER
RT CLOCK
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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