Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
In Figure 74, a noise burst makes the majority of data samples RT8,
RT9, and RT10 high. This sets the noise flag but does not reset the RT
clock. In start bits only, the RT8, RT9, and RT10 data samples are
ignored.
Figure 74 Start Bit Search Example 6
Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming frame, it sets the framing error flag, FE, in SCI
status register 1 (SCISR1). A break character also sets the FE flag
because a break character has no stop bit. The FE flag is set at the same
time that the RDRF flag is set.
Baud Rate
Tolerance
A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples (RT8, RT9, and RT10) to fall
outside the actual stop bit. A noise error will occur if the RT8, RT9, and
RT10 samples are not all the same logical values. A framing error will
occur if the receiver clock is misaligned in such a way that the majority
of the RT8, RT9, and RT10 stop bit samples are a logic zero.
As the receiver samples an incoming frame, it re-synchronizes the RT
clock on any valid falling edge within the frame. Resynchronization
within frames will correct a misalignment between transmitter bit times
and receiver bit times.
RESET RT CLOCK
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT2
RT3
RT4
RT7
RT6
RT5
RT10
RT9
RT8
RT14
RT13
RT12
RT11
RT15
RT16
RT1
RT2
RT3
SAMPLES
RT CLOCK
RT CLOCK COUNT
START BIT
sci_rx_ind
11111000
LSB
11 1 1 0 110
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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