Datasheet

Serial Communications Interface (SCI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Figure 70 summarizes the results of the
start bit verification samples.
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Figure 71 summarizes the
results of the data bit samples.
Table 71 Data Bit Recovery
NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit (logic 0).
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Figure 72 summarizes the results of the stop bit
samples.
Table 70 Start Bit Verification
RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag
000 Yes 0
001 Yes 1
010 Yes 1
011 No 0
100 Yes 1
101 No 0
110 No 0
111 No 0
RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag
000 0 0
001 0 1
010 0 1
011 1 1
100 0 1
101 1 1
110 1 1
111 1 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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