Datasheet

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Character
Reception
During an SCI reception, the receive shift register shifts a frame in from
the sci_rx_ind signal. The SCI data register is the read-only buffer
between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data
portion of the frame transfers to the SCI data register. The receive data
register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
indicating that the received byte can be read. If the receive interrupt
enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF
flag generates an RDRF interrupt request.
Data Sampling The receiver samples the sci_rx_ind signal at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock (see Figure 68) is
re-synchronized:
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
Figure 68 Receiver Data Sampling
RESET RT CLOCK
RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT8 RT7 RT6
RT11 RT10
RT9
RT15 RT14 RT13 RT12 RT16
RT1 RT2 RT3 RT4
SAMPLES
RT CLOCK
RT CLOCK COUNT
START BIT
sci_rx_ind
START BIT
QUALIFICATION
START BIT DATA
SAMPLING
111111110000000
LSB
VERIFICATION
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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