Datasheet

Serial Communications Interface (SCI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of
the stop bit of the previous frame.
Writing the TE bit from 0 to a 1 automatically loads the transmit shift
register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1).
After the preamble shifts out, control logic transfers the data from the
SCI data register into the transmit shift register. A logic 0 start bit
automatically goes into the least significant bit position of the transmit
shift register. A logic 1 stop bit goes into the most significant bit position.
Hardware supports odd or even parity. When parity is enabled, the most
significant bit (msb) of the data character is the parity bit.
The transmit data register empty flag, TDRE, in SCI status register 1
(SCISR1) becomes set when the SCI data register transfers a byte to the
transmit shift register. The TDRE flag indicates that the SCI data register
can accept new data from the internal data bus. If the transmit interrupt
enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE
flag generates a transmitter interrupt request.
When the transmit shift register is not transmitting a frame, the
sci_tx_do signal goes to the idle condition, logic 1. If at any time
software clears the TE bit in SCI control register 2 (SCICR2), the
transmitter enable signal goes low and the transmit signal goes idle.
If software clears TE while a transmission is in progress (TC = 0), the
frame in the transmit shift register continues to shift out. Then the
sci_tx_port_en signal is de-asserted and the sci_tx_do signal goes
idle even if there is data pending in the SCI data register. To avoid
accidentally cutting off the last frame in a message, always wait for
TDRE to go high after the last frame before clearing TE.
To separate messages with preambles of minimum idle line time, use
this sequence between messages:
1. Write the last byte of the first message to SCIDRH/L.
2. Wait for the TDRE flag to go high, indicating the transfer of the last
frame to the transmit shift register.
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to SCIDRH/L.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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