Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the
write-only buffers between the internal data bus and the transmit shift
register.
The SCI also sets a flag, the transmit data register empty flag (TDRE),
every time it transfers data from the buffer (SCIDRH/L) to the transmitter
shift register.The transmit driver routine may respond to this flag by
writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while
the shift register is still shifting out the first byte.
To initiate an SCI transmission:
4. Configure the SCI:
a. Select a baud rate. Write this value to the SCI baud registers
(SCIBDH/L) to begin the baud rate generator. Remember that
the baud rate generator is disabled when the baud rate is
zero. Writing to the SCIBDH has no effect without also writing
to SCIBDL.
b. Write to SCICR1 to configure word length, parity, and other
configuration bits (LOOPS, RSRC, M, WAKE, ILT, PE, PT).
c. Enable the transmitter, interrupts, receive, and wake up as
required, by writing to the SCICR2 register bits (TIE, TCIE,
RIE, ILIE, TE, RE, RWU, SBK). A preamble or idle character
will now be shifted out of the transmitter shift register.
5. Transmit Procedure for Each Byte:
a. Poll the TDRE flag by reading the SCISR1 or responding to
the TDRE interrupt. Keep in mind that the TDRE bit resets to
one.
b. If the TDRE flag is set, write the data to be transmitted to
SCIDRH/L, where the ninth bit is written to the T8 bit in
SCIDRH if the SCI is in 9-bit data format. A new transmission
will not result until the TDRE flag has been cleared.
6. Repeat step 2 for each subsequent transmission.
NOTE:
The TDRE flag is set when the shift register is loaded with the next data
to be transmitted from SCIDRH/L, which happens, generally speaking, a
little over half-way through the stop bit of the previous frame.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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