Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Transmitter
Figure 66 Transmitter Block Diagram
Transmitter
Character Length
The SCI transmitter can accommodate either 8-bit or 9-bit data
characters. The state of the M bit in SCI control register 1 (SCICR1)
determines the length of data characters. When transmitting 9-bit data,
bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
Character
Transmission
To transmit data, the MCU writes the data bits to the SCI data registers
(SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift
register. The transmit shift register then shifts a frame out through the
sci_tx_do signal, after it has prefaced it with a start bit and appended it
PE
PT
H876543210L
11-BIT TRANSMIT SHIFT REGISTER
STOP
START
T8
TDRE
TIE
TCIE
SBK
TC
PARITY
GENERATION
MSB
SCI DATA REGISTERS
LOAD FROM SCIDR
SHIFT ENABLE
PREAMBLE (ALL ONES)
BREAK (ALL 0s)
TRANSMITTER CONTROL
M
INTERNAL BUS
SBR12–SBR0
BAUD DIVIDER
÷ 16
TDRE INTERRUPT REQUEST
TC INTERRUPT REQUEST
MODULE
LOOP
RSRC
CLOCK
TE
TO
CONTROL
RECEIVER
sci_tx_port_en
LOOPS
sci_tx_do
sci_tx_obe
BRK13
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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