Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit
data characters. A frame with nine data bits has a total of 11 bits.
When the SCI is configured for 9-bit data characters, the ninth data bit is
the T8 bit in SCI data register high (SCIDRH). It remains unchanged
after transmission and can be used repeatedly without rewriting it. A
frame with nine data bits has a total of 11 bits.
Table 68 Example of 9-Bit Data Formats
Baud Rate
Generation
A 13-bit modulus counter in the baud rate generator derives the baud
rate for both the receiver and the transmitter. The value from 0 to 8191
written to the SBR12–SBR0 bits determines the module clock divisor.
The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL).
The baud rate clock is synchronized with the bus clock and drives the
receiver. The baud rate clock divided by 16 drives the transmitter. The
receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to two sources of error:
• Integer division of the module clock may not give the exact target
frequency.
Table 67 Example of 8-bit Data Formats
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
18001
17011
17
1
(1)
1. The address bit identifies the frame as an address
character. See section on Receiver Wakeup.
01
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
19001
18011
18
1
(1)
1. The address bit identifies the frame as an address
character. See section on Receiver Wakeup.
01
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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