Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Register Descriptions
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
SCI Data Registers
(SCIDRH/L)
Read: anytime; reading accesses SCI receive data register
Write: anytime; writing accesses SCI transmit data register; writing to R8
has no effect
R8 — Received Bit 8
R8 is the ninth data bit received when the SCI is configured for 9-bit
data format (M = 1).
T8 — Transmit Bit 8
T8 is the ninth data bit transmitted when the SCI is configured for 9-bit
data format (M = 1).
R7–R0 — Received bits seven through zero for 9-bit or 8-bit data
formats
T7–T0 — Transmit bits seven through zero for 9-bit or 8-bit formats
NOTE:
If the value of T8 is the same as in the previous transmission, T8 does
not have to be rewritten. The same value is transmitted until T8 is
rewritten.
Address Offset: $006
7 6 5 4 3 2 1 0
R R8
T8
0 0 0 0 0 0
W
RESET: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Address Offset: $007
7 6 5 4 3 2 1 0
R R7 R6 R5 R4 R3 R2 R1 R0
W T7 T6 T5 T4 T3 T2 T1 T0
RESET: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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