Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
SCI Status Register
2 (SCISR2)
Read: anytime
Write: anytime; writing accesses SCI status register 2; writing to any bits
except TXDIR and BRK13 has no effect
BRK13 — Break Transmit character length
This bit determines whether the transmit break character is 10 or 11
bit respectively 13 or 14 bits long. The detection of a framing error is
not affected by this bit.
1 = Break character is 13 or 14 bit long
0 = Break Character is 10 or 11 bit long
TXDIR — Transmitter pin data direction in Single-Wire mode.
This bit determines whether the TXD pin is going to be used as an
input or output, in the Single-Wire mode of operation. This bit is only
relevant in the Single-Wire mode of operation.
1 = TXD pin to be used as an output in Single-Wire mode
0 = TXD pin to be used as an input in Single-Wire mode
RAF — Receiver Active Flag
RAF is set when the receiver detects a logic 0 during the RT1 time
period of the start bit search. RAF is cleared when the receiver
detects an idle character.
1 = Reception in progress
0 = No reception in progress
Address Offset: $005
7 6 5 4 3 2 1 0
R 0 0 0 0 0
BRK13 TXDIR
RAF
W
RESET: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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