Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Register Descriptions
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
OR — Overrun Flag
OR is set when software fails to read the SCI data register before the
receive shift register receives the next frame. The OR bit is set
immediately after the stop bit has been completely received for the
second frame. The data in the shift register is lost, but the data
already in the SCI data registers is not affected. Clear OR by reading
SCI status register 1 (SCISR1) with OR set and then reading SCI data
register low (SCIDRL).
1 = Overrun
0 = No overrun
NF — Noise Flag
NF is set when the SCI detects noise on the receiver input. NF bit is
set during the same cycle as the RDRF flag but does not get set in the
case of an overrun. Clear NF by reading SCI status register 1
(SCISR1) and then reading SCI data register low (SCIDRL).
1 = Noise
0 = No noise
FE — Framing Error Flag
FE is set when a logic 0 is accepted as the stop bit. FE bit is set during
the same cycle as the RDRF flag, but does not get set in the case of
an overrun. FE inhibits further data reception until it is cleared. Clear
FE by reading SCI status register 1 (SCISR1) with FE set and then
reading the SCI data register low (SCIDRL).
1 = Framing error
0 = No framing error
PF — Parity Error Flag
PF is set when the parity enable bit, PE, is set and the parity of the
received data does not match its parity bit. Clear PF by reading SCI
status register 1 (SCISR1), and then reading SCI data register low
(SCIDRL).
1 = Parity error
0 = No parity error
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...