Datasheet

Serial Communications Interface (SCI)
Register Descriptions
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
SBK — Send Break Bit
Toggling SBK sends one break character (10 or 11 logic 0s,
respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies
clearing the SBK bit before the break character has finished
transmitting. As long as SBK is set, the transmitter continues to send
complete break characters (10 or 11, respectively 13 or 14 bits).
1 = Transmit break characters
0 = No break characters
SCI Status
Register 1(SCISR1)
The SCISR1 and SCISR2 register provides inputs to the MCU for
generation of SCI interrupts. Also, these registers can be polled by the
MCU to check the status of these bits. The flag-clearing procedures
require that the status register be read followed by a read or write to the
SCI Data Register. It is permissible to execute other instructions
between the two steps as long as it does not compromise the handling
of I/O, but the order of operations is important for flag clearing.
Read: anytime
Write: has no meaning or effect
TDRE — Transmit Data Register Empty Flag
TDRE is set when the transmit shift register receives a byte from the
SCI data register. When TDRE is 1, the transmit data register
(SCIDRH/L) is empty and can receive a new value to transmit. Clear
TDRE by reading SCI status register 1 (SCISR1) with TDRE set and
then writing to SCI data register low (SCIDRL).
1 = Byte transferred to transmit shift register; transmit data register
empty
0 = No byte transferred to transmit shift register
Address Offset: $004
7 6 5 4 3 2 1 0
R TDRE TC RDRF IDLE OR NF FE PF
W
RESET: 1 1 0 0 0 0 0 0
= Unimplemented or Reserved
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