Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Central Processing Unit (CPU)
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
TSX Transfer SP to X; (SP)⇒X;
assembles as TFR SP,X
INH B7 75 P
TSY Transfer SP to Y; (SP)⇒Y;
assembles as TFR SP,Y
INH B7 76 P
TXS Transfer X to SP; (X)⇒SP;
assembles as TFR X,SP
INH B7 57 P
TYS Transfer Y to SP; (Y)⇒SP;
assembles as TFR Y,SP
INH B7 67 P
WAI Wait for interrupt; (SP)–2⇒SP;
RTN
H
:RTN
L
⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (Y
H
:Y
L
)⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (X
H
:X
L
)⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (B:A)⇒M
SP
:M
SP+1
;
(SP)–1⇒SP; (CCR)⇒M
SP
INH 3E OSSSSsf
(before interrupt)
fVfPPP
(after interrupt)
or
or
WAV Calculate weighted average; sum of
products (SOP) and sum of weights
(SOW)*
Special 18 3C Of(frr^ffff)O**
SSS+UUUrr^***
*Initialize B, X, and Y: B= number of elements; X points at first element in S
i
list; Y points at first element in F
i
list. All S
i
and F
i
elements are 8-bit values.
**The frr^ffff sequence is the loop for one iteration of SOP and SOW accumulation. The ^ denotes a check for pending interrupt requests.
***These are additional cycles caused by an interrupt: SSS is the exit sequence and UUUrr^ is the re-entry sequence. Intermediate values use six
stack bytes.
wavr* Resume executing interrupted WAV Special 3C UUUrr^ffff(frr^
ffff)O**
SSS+UUUrr^***
*wavr is a pseudoinstruction that recovers intermediate results from the stack rather than initializing them to 0.
**The frr^ffff sequence is the loop for one iteration of SOP and SOW recovery. The ^ denotes a check for pending interrupt requests.
***These are additional cycles caused by an interrupt: SSS is the exit sequence and UUUrr^ is the re-entry sequence.
XGDX Exchange D with X; (D)⇔(X);
assembles as EXG D, X
INH B7 C5 P
XGDY Exchange D with Y; (D)⇔(Y);
assembles as EXG D, Y
INH B7 C6 P
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––––––
––––––––
––––––––
––––––––
––––––––
–––1––––
–1–1––––
F
i
i1=
B
∑
X⇒
S
i
F
i
i1=
B
∑
Y:D⇒
––?–?∆ ??
––?–?∆ ??
––––––––
––––––––
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...