Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Register Descriptions
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
PE — Parity Enable Bit
PE enables the parity function. When enabled, the parity function
inserts a parity bit in the most significant bit position.
1 = Parity function enabled
0 = Parity function disabled
PT — Parity Type Bit
PT determines whether the SCI generates and checks for even parity
or odd parity. With even parity, an even number of 1s clears the parity
bit and an odd number of 1s sets the parity bit. With odd parity, an odd
number of 1s clears the parity bit and an even number of 1s sets the
parity bit.
1 = Odd parity
0 = Even parity
SCI Control
Register 2
(SCICR2)
Read: anytime
Write: anytime
TIE — Transmitter Interrupt Enable Bit
TIE enables the transmit data register empty flag, TDRE, to generate
interrupt requests.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
Address Offset: $003
7 6 5 4 3 2 1 0
R
TIE TCIE RIE ILIE TE RE RWU SBK
W
RESET: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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