Datasheet

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
0 = SCI enabled in wait mode
RSRC — Receiver Source Bit
When LOOPS = 1, the RSRC bit determines the source for the
receiver shift register input.
1 = Receiver input connected externally to transmitter
0 = Receiver input internally connected to transmitter output
M — Data Format Mode Bit
MODE determines whether data characters are eight or nine bits
long.
1 = One start bit, nine data bits, one stop bit
0 = One start bit, eight data bits, one stop bit
WAKE — Wakeup Condition Bit
WAKE determines which condition wakes up the SCI: a logic 1
(address mark) in the most significant bit position of a received data
character or an idle condition on the sci_rx_ind.
1 = Address mark wakeup
0 = Idle line wakeup
ILT — Idle Line Type Bit
ILT determines when the receiver starts counting logic 1s as idle
character bits. The counting begins either after the start bit or after the
stop bit. If the count begins after the start bit, then a string of logic 1s
preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
Table 66 Loop Functions
LOOPS RSRC Function
0 x Normal operation
1 0 Loop mode with Rx input internally connected to Tx output
1 1 Single-wire mode with Rx input connected to sci_tx_ind
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...