Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Register Descriptions
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Write: anytime
SBR12–SBR0 — SCI Baud Rate Bits
The baud rate for the SCI is determined by these 13 bits.
NOTE:
The baud rate generator is disabled until the TE bit or the RE bit is set
for the first time after reset. The baud rate generator is disabled when
BR = 0.
NOTE:
Writing to SCIBDH has no effect without writing to SCIBDL, since writing
to SCIBDH puts the data in a temporary location until SCIBDL is written
to.
SCI Control
Register 1
Read: anytime
Write: anytime
LOOPS — Loop Select Bit
LOOPS enables loop operation. In loop operation, the RXD pin is
disconnected from the SCI and the transmitter output is internally
connected to the receiver input. Both the transmitter and the receiver
must be enabled to use the loop function.
1 = Loop operation enabled
0 = Normal operation enabled
The receiver input is determined by the RSRC bit.
SCISWAI — SCI Stop in Wait Mode Bit
SCISWAI disables the SCI in wait mode.
1 = SCI disabled in wait mode
Address Offset: $002
7 6 5 4 3 2 1 0
R
LOOPS SCISWAI RSRC M WAKE ILT PE PT
W
RESET: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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