Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Register Descriptions
This section consists of register descriptions in address order. Each
description includes a standard register diagram with an associated
figure number. Writes to a reserved register location do not have any
effect and reads of these locations return a zero. Details of register bit
and field function follow the register diagrams, in bit order.
SCI Baud Rate
Registers
(SCIBDH/L)
The SCI Baud Rate Register is used by the counter to determine the
baud rate of the SCI. The formula for calculating the baud rate is:
SCI baud rate = SCI module clock / (16 x BR),
where BR is the content of the SCI baud rate registers, bits SBR12
through SBR0. The baud rate registers can contain a value from 1 to
8191.
Read: anytime. A read will not return the correct data if only SCIBDH is
written to. SCIBDL must also be written to, following a write to SCIBDH.
Address Offset: $000
7 6 5 4 3 2 1 0
R 0 0 0
SBR12 SBR11 SBR10 SBR9 SBR8
W
RESET: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Address Offset: $001
7 6 5 4 3 2 1 0
R
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
RESET: 0 0 0 0 0 1 0 0
= Unimplemented or Reserved
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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