Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
Register Quick Reference
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
Register Quick Reference
Figure 64 SCI Register Quick Reference
Register name Bit 7 654321Bit 0
Addr.
offset
SCIBDH
Read: 0 0 0
SBR12 SBR11 SBR10 SBR9 SBR8 $000
Write:
SCIBDL
Read:
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 $001
Write:
SCICR1
Read:
LOOPS SCISWAI RSRC M WAKE ILT PE PT $002
Write:
SCICR2
Read:
TIE TCIE RIE ILIE TE RE RWU SBK $003
Write:
SCISR1
Read: TDRE TC RDRF IDLE OR NF FE PF
$004
Write:
SCISR2
Read: 0 0000
BRK13 TXDIR
RAF
$005
Write:
SCIDRH
Read: R8
T8
000000
$006
Write:
SCIDRL
Read: R7 R6 R5 R4 R3 R2 R1 R0
$007
Write: T7 T6 T5 T4 T3 T2 T1 T0
= Reserved or unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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