Datasheet

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
sci_tx_obe If the pad is controlled by the SCI, then this signal determines whether
the SCI will drive sci_tx_do.
Interrupt Signal The SCI has one interrupt signal. Refer to the Interrupt Operation
subsection for more details.
Module Memory Map
The memory map for the SCI module is given below in Table 65. The
Address listed for each register is the address offset. The total address
for each register is the sum of the base address for the SCI module and
the address offset for each register.
Table 65 Module Memory Map
Offset Use Access
$000
SCI Baud Rate Register High (SCIBDH)
Read/Write
$001
SCI Baud Rate Register Low (SCIBDL)
Read/Write
$002
SCI Control Register1 (SCICR1)
Read/Write
$003
SCI Control Register 2 (SCICR2)
Read/Write
$004
SCI Status Register 1 (SCISR1)
Read
$005
SCI Status Register 2(SCISR2)
Read/Write
$006
SCI Data Register High (SCIDRH)
Read/Write
$007
SCI Data Register Low (SCIDRL)
Read/Write
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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