Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Communications Interface (SCI)
MC9S12DP256 — Revision 1.1
Serial Communications Interface (SCI)
SCI Interface Diagram
Block Diagram
Figure 63 is a block diagram of the SCI.
Figure 63 SCI Block Diagram
SCI DATA
RECEIVE
SHIFT REGISTER
SCI DATA
REGISTER
TRANSMIT
SHIFT REGISTER
REGISTER
BAUD RATE
GENERATOR
SBR12–SBR0
sci_rx_ind
sci_tx_do
MODULE
TRANSMIT
CONTROL
÷16
RECEIVE
AND WAKEUP
DATA FORMAT
CONTROL
CONTROL
T8
PF
FE
NF
RDRF
IDLE
TIE
OR
TCIE
TDRE
TC
R8
RAF
LOOPS
RWU
RE
PE
ILT
PT
WAKE
M
CLOCK
IDLE
ILIE
RIE
RDRF/OR
TDRE
TC
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
RSRC
SBK
LOOPS
TE
RSRC
REQUEST
REQUEST
REQUEST
REQUEST
BRK13
TXDIR
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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