Datasheet

Central Processing Unit (CPU)
Instruction Set Summary
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
SUBB # opr8i
SUBB opr8a
SUBB opr16a
SUBB oprx0_xysppc
SUBB oprx9 , xysppc
SUBB oprx16 , xysppc
SUBB [D, xysppc ]
SUBB [ oprx16 , xysppc ]
Subtract from B; (B)–(M)⇒B or
(B)–imm⇒B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C0 ii
D0 dd
F0 hh ll
E0 xb
E0 xb ff
E0 xb ee ff
E0 xb
E0 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
SUBD # opr16i
SUBD opr8a
SUBD opr16a
SUBD oprx0_xysppc
SUBD oprx9 , xysppc
SUBD oprx16 , xysppc
SUBD [D, xysppc ]
SUBD [ oprx16 , xysppc ]
Subtract from D;
(A:B)–(M:M+1)⇒A:B or
(A:B)–imm⇒A:B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
83 jj kk
93 dd
B3 hh ll
A3 xb
A3 xb ff
A3 xb ee ff
A3 xb
A3 xb ee ff
PO
RPf
RPO
RPf
RPO
fRPP
fIfRPf
fIPRPf
SWI Software interrupt; (SP)–2⇒SP;
RTN
H
:RTN
L
⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (Y
H
:Y
L
)⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (X
H
:X
L
)⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (B:A)⇒M
SP
:M
SP+1
;
(SP)–1⇒SP; (CCR)⇒M
SP
;1⇒I;
(SWI vector)⇒PC
INH 3F VSPSSPSsP*
*The CPU also uses VSPSSPSsP for hardware interrupts and unimplemented opcode traps. Reset uses a variation of VfPPP.
TAB Transfer A to B; (A)⇒B INH 18 0E OO
TAP Transfer A to CCR; (A)⇒CCR;
assembled as TFR A, CCR
INH B7 02 P
TBA Transfer B to A; (B)⇒A INH 18 0F OO
TBEQ
abdxysp , rel9 Test and branch if equal to 0; if
(register)=0, then (PC)+2+rel⇒PC
REL
(9-bit)
04 lb rr PPP (branch)
PPO (no branch)
TBL oprx0_xysppc Table lookup and interpolate, 8-bit;
(M)+[(B)×((M+1)–(M))]⇒A
IDX 18 3D xb ORfffP
TBNE abdxysp , rel9 Test and branch if not equal to 0; if
(register)≠0, then (PC)+2+rel⇒PC
REL
(9-bit)
04 lb rr PPP (branch)
PPO (no branch)
TFR abcdxysp , abcdxysp Transfer register to register;
(r1)⇒r2; r1 and r2 same size or
$00:(r1)⇒r2; r1=8-bit; r2=16-bit or
(r1
L
)⇒r2; r1=16-bit; r2=8-bit
INH B7 eb P
or
TPA Transfer CCR to A; (CCR)⇒A;
assembles as TFR CCR ,A
INH B7 20 P
TRAP
trapnum Trap unimplemented opcode;
(SP)–2⇒SP;
RTN
H
:RTN
L
⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (Y
H
:Y
L
)⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (X
H
:X
L
)⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (B:A)⇒M
SP
:M
SP+1
;
(SP)–1⇒SP; (CCR)⇒M
SP
;
1⇒I; (trap vector)⇒PC
INH 18 tn
tn = $30–$39
or
tn = $40–$FF
OVSPSSPSsP
TST
opr16a
TST oprx0_xysppc
TST oprx9 , xysppc
TST oprx16 , xysppc
TST [D, xysppc ]
TST [ oprx16 , xysppc ]
TSTA
TSTB
Test M; (M)–0
Test A; (A)–0
Test B; (B)–0
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
F7 hh ll
E7 xb
E7 xb ff
E7 xb ee ff
E7 xb
E7 xb ee ff
97
D7
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
O
O
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––∆∆∆∆
––––∆∆∆∆
–––1––––
––––∆∆0–
∆
⇓
∆∆∆∆∆∆
––––∆∆0–
––––––––
––––∆∆– ∆
––––––––
––––––––
∆
⇓
∆∆∆∆∆∆
––––––––
–––1––––
––––∆∆00
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Freescale Semiconductor, Inc.
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