Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
If modulus mode is not enabled (MODMC=0), a write to this address will
clear the prescaler and will immediately update the counter register with
the value written to it and down-counts once to $0000
Timer Input
Capture Holding
Registers 0Ð3
(TC0HÐTC3H)
Read: any time
Write: has no effect.
These registers are used to latch the value of the input capture registers
TC0–TC3. The corresponding IOSx bits in TIOS ($00) should be cleared
(see IC Channels).
Register offset: $0038–$003F
TC0H Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TC1H Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TC2H Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TC3H Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
RESET 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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