Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPAR ($28) are enabled
(see Pulse Accumulators).
Modulus
Down-Counter
Count Register
(MCCNT)
Read or write any time.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
bit is set, reads of the MCCNT will return the contents of the load
register.
If a $0000 is written into MCCNT and modulus counter while LATQ and
BUFEN in ICSYS ($2B) register are set, the input capture and pulse
accumulator registers will be latched.
With a $0000 write to the MCCNT, the modulus counter will stay at zero
and does not set the MCZF flag in MCFLG register.
If modulus mode is enabled (MODMC=1), a write to this address will
update the load register with the value written to it. The count register will
not be updated with the new value until the next counter underflow.
The FLMC bit in MCCTL ($26) can be used to immediately update the
count register with the new value if an immediate load is desired.
Register offset: $0036–$0037
BIt 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
RESET: 1 1 1 1 1 1 1 1
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