Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Pulse Accumulator
B Flag Register
(PBFLG)
Read or write any time.
PBOVF — Pulse Accumulator B Overflow Flag
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows
from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF
flag in this register when TFFCA bit in register TSCR($06) is set.
When PACMX=1, PBOVF bit can also be set if 8-bit pulse
accumulator 1 (PAC1) reaches $FF and followed an active edge
comes on PT1.
8-Bit Pulse
Accumulators
Holding Registers
(PA3HÐPA0H)
Read: any time
Write: has no effect.
Register offset: $0031
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 0 0 PBOVF 0
RESET: 0 0 0 0 0 0 0 0
Register offset: $0032–$0035
PA3H BIt 7 6 5 4 3 2 1 Bit 0
PA2H Bit 7 6 5 4 3 2 1 Bit 0
PA1H BIt 7 6 5 4 3 2 1 Bit 0
PA0H Bit 7 6 5 4 3 2 1 Bit 0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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