Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Central Processing Unit (CPU)
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
STAA
opr8a
STAA
opr16a
STAA
oprx0_xysppc
STAA
oprx9
,
xysppc
STAA
oprx16
,
xysppc
STAA [D,
xysppc
]
STAA [
oprx16
,
xysppc
]
Store accumulator A; (A)⇒M DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5A dd
7A hh ll
6A xb
6A xb ff
6A xb ee ff
6A xb
6A xb ee ff
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
STAB
opr8a
STAB
opr16a
STAB
oprx0_xysppc
STAB
oprx9
,
xysppc
STAB
oprx16
,
xysppc
STAB [D,
xysppc
]
STAB [
oprx16
,
xysppc
]
Store accumulator B; (B)⇒M DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5B dd
7B hh ll
6B xb
6B xb ff
6B xb ee ff
6B xb
6B xb ee ff
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
STD
opr8a
STD
opr16a
STD
oprx0_xysppc
STD
oprx9
,
xysppc
STD
oprx16
,
xysppc
STD [D,
xysppc
]
STD [
oprx16
,
xysppc
]
Store D; (A:B)⇒M:M+1 DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5C dd
7C hh ll
6C xb
6C xb ff
6C xb ee ff
6C xb
6C xb ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
STOP Stop processing; (SP)–2⇒SP;
RTN
H
:RTN
L
⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (Y
H
:Y
L
)⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (X
H
:X
L
)⇒M
SP
:M
SP+1
;
(SP)–2⇒SP; (B:A)⇒M
SP
:M
SP+1
;
(SP)–1⇒SP; (CCR)⇒M
SP
;
stop all clocks
INH 18 3E OOSSSSsf (enter
stop mode)
fVfPPP (exit stop
mode)
ff (continue stop
mode)
OO (if stop mode
disabled by S=1)
STS
opr8a
STS
opr16a
STS
oprx0_xysppc
STS
oprx9
,
xysppc
STS
oprx16
,
xysppc
STS [D,
xysppc
]
STS [
oprx16
,
xysppc
]
Store SP; (SP
H
:SP
L
)⇒M:M+1 DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5F dd
7F hh ll
6F xb
6F xb ff
6F xb ee ff
6F xb
6F xb ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
STX
opr8a
STX
opr16a
STX
oprx0_xysppc
STX
oprx9
,
xysppc
STX
oprx16
,
xysppc
STX [D,
xysppc
]
STX [
oprx16
,
xysppc
]
Store X; (X
H
:X
L
)⇒M:M+1 DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5E dd
7E hh ll
6E xb
6E xb ff
6E xb ee ff
6E xb
6E xb ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
STY
opr8a
STY
opr16a
STY
oprx0_xysppc
STY
oprx9
,
xysppc
STY
oprx16
,
xysppc
STY [D,
xysppc
]
STY [
oprx16
,
xysppc
]
Store Y; (Y
H
:Y
L
)⇒M:M+1 DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
5D dd
7D hh ll
6D xb
6D xb ff
6D xb ee ff
6D xb
6D xb ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
SUBA #
opr8i
SUBA
opr8a
SUBA
opr16a
SUBA
oprx0_xysppc
SUBA
oprx9
,
xysppc
SUBA
oprx16
,
xysppc
SUBA [D,
xysppc
]
SUBA [
oprx16
,
xysppc
]
Subtract from A; (A)–(M)⇒A or
(A)–imm⇒A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
80 ii
90 dd
B0 hh ll
A0 xb
A0 xb ff
A0 xb ee ff
A0 xb
A0 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––––––
––––∆∆0–
––––∆∆0–
––––∆∆0–
––––∆∆∆∆
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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