Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
16-Bit Pulse
Accumulator B
Control Register
(PBCTL)
Read or write any time.
16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit
pulse accumulators PAC1 and PAC0.
When PBEN is set, the PACB is enabled. The PACB shares the input pin
with IC0.
PBEN — Pulse Accumulator B System Enable
1 = Pulse Accumulator B system enabled. The two 8-bit pulse
accumulators PAC1 and PAC0 are cascaded to form the
PACB 16-bit pulse accumulator. When PACB in enabled, the
PACN1 and PACN0 registers contents are respectively the
high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPAR ($28) have no effect.
0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and
PAC0 can be enabled when their related enable bits in ICPAR
($28) are set.
PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
PBOVI — Pulse Accumulator B Overflow Interrupt enable
1 = interrupt requested if PBOVF is set
0 = interrupt inhibited
Register offset: $0030
Bit 7 6 5 4 3 2 1 Bit 0
0 PBEN 0 0 0 0 PBOVI 0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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