Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
With a latching event the contents of IC registers and 8-bit
pulse accumulators are transferred to their holding registers.
8-bit pulse accumulators are cleared.
0 = Queue Mode of Input Capture is enabled.
The main timer value is memorized in the IC register by a valid
input pin transition.
With a new occurrence of a capture, the value of the IC register
will be transferred to its holding register and the IC register
memorizes the new timer value.
Timer Test Register
(TIMTST)
Read: any time
Write: only in special mode (test_mode = 1).
TCBYP — Main Timer Divider Chain Bypass
1 = For testing only. The 16-bit free-running timer counter is divided
into two 8-bit halves and the prescaler is bypassed. The clock
drives both halves directly.
When the high byte of timer counter TCNT ($04) overflows
from $FF to $00, the TOF flag in TFLG2 ($0F) will be set.
0 = Normal operation
Register offset: $002D
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 0 0 TCBYP 0
RESET 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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