Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
In all other input capture cases the interrupt flag is set by a valid
external event on PTn.
1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags
C3F–C0F in TFLG1 ($0E) are set only when a latch on the
corresponding holding register occurs.
If the queue mode is not engaged, the timer flags C3F–C0F are
set the same way as for TFMOD=0.
0 = The timer flags C3F–C0F in TFLG1 ($0E) are set when a valid
input capture transition on the corresponding port pin occurs.
PACMX — 8-Bit Pulse Accumulators Maximum Count
1 = When the 8-bit pulse accumulator has reached the value $FF,
it will not be incremented further. The value $FF indicates a
count of 255 or more.
0 = Normal operation. When the 8-bit pulse accumulator has
reached the value $FF, with the next active edge, it will be
incremented to $00.
BUFEN — IC Buffer Enable
1 = Input Capture and pulse accumulator holding registers are
enabled. The latching mode is defined by LATQ control bit.
Write one into ICLAT bit in MCCTL ($26), when LATQ is set will
produce latching of input capture and pulse accumulators
registers into their holding registers.
0 = Input Capture and pulse accumulator holding registers are
disabled.
LATQ — Input Control Latch or Queue Mode Enable
The BUFEN control bit should be set in order to enable the IC and
pulse accumulators holding registers. Otherwise LATQ latching
modes are disabled.
Write one into ICLAT bit in MCCTL ($26), when LATQ and BUFEN
are set will produce latching of input capture and pulse accumulators
registers into their holding registers.
1 = Latch Mode is enabled. Latching function occurs when
modulus down-counter reaches zero or a zero is written into
the count register MCCNT (see Buffered IC Channels).
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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