Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
NOVWx — No Input Capture Overwrite
1 = The related capture register or holding register cannot be
written by an event unless they are empty (see IC Channels).
This will prevent the captured value to be overwritten until it is
read or latched in the holding register.
0 = The contents of the related capture register or holding register
can be overwritten when a new input capture or latch occurs.
Input Control
System Control
Register (ICSYS)
Read: any time
Write: May be written once (test_mode =0). Writes are always permitted
when test_mode =1.
SHxy — Share Input action of Input Capture Channels x and y
1 = The channel input ‘x’ causes the same action on the channel
‘y’. The port pin ‘x’ and the corresponding edge detector is
used to be active on the channel ‘y’.
0 = Normal operation
TFMOD — Timer Flag-setting Mode
Use of the TFMOD bit in the ICSYS register ($2B) in conjunction with
the use of the ICOVW register ($2A) allows a timer interrupt to be
generated after capturing two values in the capture and holding
registers instead of generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVW bit is set and the
corresponding capture and holding registers are emptied, an input
capture event will first update the related input capture register with
the main timer contents. At the next event the TCn data is transferred
to the TCnH register, The TCn is updated and the CnF interrupt flag
is set. See Figure 58.
Register offset: $002B
Bit 7 6 5 4 3 2 1 Bit 0
SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ
RESET: 0 0 0 0 0 0 0 0
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