Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
If enabled, after detection of a valid edge on input capture pin, the delay
counter counts the pre-selected number of M clock (module clock)
cycles, then it will generate a pulse on its output. The pulse is generated
only if the level of input signal, after the preset delay, is the opposite of
the level before the transition.This will avoid reaction to narrow input
pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be
longer than the selected counter delay.
DLYx — Delay Counter Select
Here ‘M’ refers to module clock.
Input Control
Overwrite Register
(ICOVW)
Read or write any time.
An IC register is empty when it has been read or latched into the holding
register.
A holding register is empty when it has been read.
Table 62 Delay Counter Select
DLY1 DLY0 Delay
0 0 Disabled (bypassed)
0 1 256M clock cycles
1 0 512M clock cycles
1 1 1024 M clock cycles
Register offset: $002A
Bit 7 6 5 4 3 2 1 Bit 0
NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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