Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Each status bit gives the polarity of the first edge which has caused
an input capture to occur after capture latch has been read.
Each POLFx corresponds to a timer PORTx input.
1 = The first input capture has been caused by a rising edge.
0 = The first input capture has been caused by a falling edge.
Input Control Pulse
Accumulators
Register (ICPAR)
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if
PAEN in PATCL ($20) is cleared. If PAEN is set, PA3EN and PA2EN
have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if
PBEN in PBTCL ($30) is cleared. If PBEN is set, PA1EN and PA0EN
have no effect.
Read or write any time.
PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable
1 = 8-Bit Pulse Accumulator is enabled.
0 = 8-Bit Pulse Accumulator is disabled.
Delay Counter
Control Register
(DLYCT)
Read or write any time.
Register offset: $0028
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 PA3EN PA2EN PA1EN PA0EN
RESET 0 0 0 0 0 0 0 0
Register offset: $0029
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 0 0 DLY1 DLY0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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