Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
When MCEN=0, the counter is preset to $FFFF. This will prevent an
early interrupt flag when the modulus down-counter is enabled.
MCPR1, MCPR0 — Modulus Counter Prescaler select
These two bits specify the division rate of the modulus counter
prescaler.
The newly selected prescaler division rate will not be effective until a
load of the load register into the modulus counter count register
occurs.
16-Bit Modulus
Down-Counter
FLAG Register
(MCFLG)
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Flag
The flag is set when the modulus down-counter reaches $0000.
A write one to this bit clears the flag. Write zero has no effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($06) is set.
POLF3–POLF0 — First Input Capture Polarity Status
This are read only bits. Write to these bits has no effect.
Table 61 Modulus Counter Prescaler Select
MCPR1 MCPR0 Prescaler division rate
00 1
01 4
10 8
11 16
Register offset: $0027
Bit 7 6 5 4 3 2 1 Bit 0
MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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