Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
Pulse
Accumulators
Count Registers
(PACN1, PACN0)
Read or write any time.
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1
in PBCTL, $30) the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG ($31) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
16ÐBit Modulus
Down-Counter
Control Register
(MCCTL)
Read or write any time.
MCZI — Modulus Counter Underflow Interrupt Enable
1 = Modulus counter interrupt is enabled.
0 = Modulus counter interrupt is disabled.
Register offset: $0024–$0025
PACN1 Bit 7 6 5 4 3 2 1 Bit 0
PACN0 Bit 7 6 5 4 3 2 1 Bit 0
RESET 0 0 0 0 0 0 0 0
Register offset: $0026
Bit 7 6 5 4 3 2 1 Bit 0
MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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