Datasheet

Central Processing Unit (CPU)
Instruction Set Summary
MC9S12DP256 — Revision 1.1
Central Processing Unit (CPU)
ROL opr16a
ROL oprx0_xysppc
ROL oprx9 , xysppc
ROL oprx16 , xysppc
ROL [D, xysppc ]
ROL [ oprx16 , xysppc ]
ROLA
ROLB
Rotate left M
Rotate left A
Rotate left B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
75 hh ll
65 xb
65 xb ff
65 xb ee ff
65 xb
65 xb ee ff
45
55
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
ROR
opr16a
ROR oprx0_xysppc
ROR oprx9 , xysppc
ROR oprx16 , xysppc
ROR [D, xysppc ]
ROR [ oprx16 , xysppc ]
RORA
RORB
Rotate right M
Rotate right A
Rotate right B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
76 hh ll
66 xb
66 xb ff
66 xb ee ff
66 xb
66 xb ee ff
46
56
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
RTC Return from call; (M
SP
)⇒PPAGE;
(SP)+1⇒SP;
(M
SP
:M
SP+1
)⇒PC
H
:PC
L
;
(SP)+2⇒SP
INH 0A uUnfPPP
RTI Return from interrupt;
(M
SP
)⇒CCR; (SP)+1⇒SP;
(M
SP
:M
SP+1
)⇒B:A;(SP)+2⇒SP;
(M
SP
:M
SP+1
)⇒X
H
:X
L
;(SP)+4⇒SP;
(M
SP
:M
SP+1
)⇒PC
H
:PC
L
;(SP)+2⇒SP;
(M
SP
:M
SP+1
)⇒Y
H
:Y
L
;(SP)+4⇒SP
INH 0B uUUUUPPP
or
uUUUUfVfPPP*
*RTI takes 11 cycles if an interrupt is pending.
RTS Return from subroutine;
(M
SP
:M
SP+1
)⇒PC
H
:PC
L
;
(SP)+2⇒SP
INH 3D UfPPP
SBA Subtract B from A; (A)–(B)⇒A INH 18 16 OO
SBCA #
opr8i
SBCA opr8a
SBCA opr16a
SBCA oprx0_xysppc
SBCA oprx9 , xysppc
SBCA oprx16 , xysppc
SBCA [D, xysppc ]
SBCA [ oprx16 , xysppc ]
Subtract with carry from A;
(A)–(M)–C⇒A or (A)–imm–C⇒A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
82 ii
92 dd
B2 hh ll
A2 xb
A2 xb ff
A2 xb ee ff
A2 xb
A2 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
SBCB # opr8i
SBCB opr8a
SBCB opr16a
SBCB oprx0_xysppc
SBCB oprx9 , xysppc
SBCB oprx16 , xysppc
SBCB [D, xysppc ]
SBCB [ oprx16 , xysppc ]
Subtract with carry from B;
(B)–(M)–C⇒B or (B)–imm–C⇒B
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
C2 ii
D2 dd
F2 hh ll
E2 xb
E2 xb ff
E2 xb ee ff
E2 xb
E2 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
SEC Set C; assembles as ORCC #$01 IMM 14 01 P
SEI Set I; assembles as ORCC #$10 IMM 14 10 P
SEV Set V; assembles as ORCC #$02 IMM 14 02 P
SEX
abc , dxysp Sign extend; 8-bit r1 to 16-bit r2;
$00:(r1)⇒r2 if r1 bit 7 is 0 or
$FF:(r1)⇒r2 if r1, bit 7 is 1;
alternate mnemonic for TFR r1, r2
INH B7 eb P
Source Form Operation
Address
Mode
Machine
Coding (Hex)
Access Detail S X H I N Z V C
C
b7
b0
––––∆∆∆∆
C
b7
b0
––––∆∆∆∆
––––––––
∆
⇓
∆∆∆∆∆∆
––––––––
––––∆∆∆∆
––––∆∆∆∆
––––∆∆∆∆
–––––––1
–––1––––
––––––1–
––––––––
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Freescale Semiconductor, Inc.
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