Datasheet

Enhanced Capture Timer (ECT)
Register Descriptions
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
PAOVI — Pulse Accumulator A Overflow Interrupt enable
1 = interrupt requested if PAOVF is set
0 = interrupt inhibited
PAI — Pulse Accumulator Input Interrupt enable
1 = interrupt requested if PAIF is set
0 = interrupt inhibited
Pulse
Accumulator A
Flag Register
(PAFLG)
Read or write anytime. When the TFFCA bit in the TSCR register is set,
any access to the PACNT register will clear all the flags in the PAFLG
register.
PAOVF — Pulse Accumulator A Overflow Flag
Set when the 16-bit pulse accumulator A overflows from $FFFF to
$0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF
to $00.
When PACMX = 1, PAOVF bit can also be set if 8-bit pulse
accumulator 3 (PAC3) reaches $FF followed by an active edge on
PT3.
This bit is cleared automatically by a write to the PAFLG register with
bit 1 set.
Register offset: $0021
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 0 0 PAOVF PAIF
RESET: 0 0 0 0 0 0 0 0
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...