Datasheet

Enhanced Capture Timer (ECT)
MC9S12DP256 — Revision 1.1
Enhanced Capture Timer (ECT)
PAMOD — Pulse Accumulator Mode
This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1).
1 = gated time accumulation mode
0 = event counter mode
PEDGE — Pulse Accumulator Edge Control
This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1).
For PAMOD bit = 0 (event counter mode).
1 = rising edges on PT7 pin cause the count to be incremented
0 = falling edges on PT7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
1 = PT7 input pin low enables M (module clock) divided by 64 clock
to Pulse Accumulator and the trailing rising edge on PT7 sets
the PAIF flag
0 = PT7 input pin high enables M (module clock) divided by 64
clock to Pulse Accumulator and the trailing falling edge on PT7
sets the PAIF flag.
Table 59 Pin Action
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
since the ÷64 clock is generated by the timer prescaler.
CLK1, CLK0 — Clock Select Bits
Table 60 Clock Selection
For the description of PACLK please refer to Figure 56.
PAMOD PEDGE Pin Action
0 0 Falling edge
0 1 Rising edge
1 0 Div. by 64 clock enabled with pin high level
1 1 Div. by 64 clock enabled with pin low level
CLK1 CLK0 Clock Source
0 0 Use timer prescaler clock as timer counter clock
0 1 Use PACLK as input to timer counter clock
1 0 Use PACLK/256 as timer counter clock frequency
1 1 Use PACLK/65536 as timer counter clock frequency
Freescale Semiconductor, I
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